In a typical block of computer memory, memory cells are arranged in rows and columns, where the memory cells in each row are accessed using one or more word lines shared by those memory cells, and the memory cells in each column are accessed using one or more bit lines shared by those memory cells. The word lines and bit lines, as well as other circuitry associated with the memory block, are controlled using control signals (e.g., word-line enable, bit-line precharge, sense-amp enable, muxed bit-line precharge, write enable) whose relative timing must be accurately controlled in order for the memory block to operate correctly. For example, in certain conventional memory blocks, the bit-line precharge control signal, which is active low, must be de-asserted prior to the word-line enable control signal being asserted, and the bit-line precharge control signal must be asserted after the word-line enable control signal has been de-asserted. Conventional memory blocks rely on pulse-generation circuits to generate various control signals with appropriate relative timing. Such pulse-generation circuits must be able to operate properly under expected ranges of process, voltage, and temperature (PVT) characteristics.
FIG. 1 shows a schematic block diagram of a conventional pulse-generation circuit 100 for generating a word-line enable control signal (WL_EN) and a bit-line precharge control signal (BL_PCHGB). Pulse-generation circuit 100 comprises clock register 102, delay block 104, delay elements 106-110, multiplexers (muxes) M1-M3, and pulse generators 112-114. Each pulse generator comprises a logical-NAND gate and two inverters. Pulse-generation circuit 100 is designed to ensure that the rising edge of each pulse in control signal BL_PCHGB leads the rising edge of the corresponding pulse in control signal WL_EN, while the falling edge of each pulse in control signal BL_PCHGB trails the falling edge of the corresponding pulse in control signal WL_EN.
Clock register 102 receives (1) the result (CS.CE) of applying the logical-AND function to a chip select (CS) signal and a clock enable (CE) signal, (2) a clock signal CLK, and (3) a reset signal RST and presents clock signal CLK at its output as registered clock signal CSE_REG, if CS.CE is high and RST is low. If either CS.CE is low or RST is high, then clock signal CLK will not be forwarded to the clock register output. Reset signal RST is used to return control signals WL_EN and BL_PCHGB to their steady-state values (i.e., 0) after the end of each read or write operation in the memory block.
Delay block 104, typically implemented as a chain of inverters, receives registered clock signal CSE_REG at its input and presents, in this exemplary situation, four delayed versions (N1, N2, N3, and N4) of that clock signal, where each delayed clock signal Ni corresponds to the output of a different inverter in delay block 104. Note that the delay of N4 is greater than the delay of N3, which is greater than the delay of N2, which is greater than the delay on N1.
Delayed clock signal N1 is applied to the 0 input of mux M2 and to the input of delay element 108, whose output is applied to the 1 input of mux M2.
Delayed clock signal N2 is applied to one of the inputs of NAND gate 116 in pulse generator 112.
Delayed clock signal N3 is applied to the 0 input of mux M1 and to the input of delay element 106, whose output is applied to the 1 input of mux M1.
Delayed clock signal N4 is applied to the 0 input of mux M3 and to the input of delay element 110, whose output is applied to the 1 input of mux M3.
Muxes M1-M3 are individually controlled by configuration fuses F1-F3, respectively, to select either the corresponding delayed clock signal N1 or a further delayed version of that delayed clock signal, for forwarding to the corresponding pulse generator. Delay elements 106-110 and muxes M1-M3 provide programmable flexibility in the selection of the various delays generated by delay block 104. Note that the outputs of muxes M1 and M3 are inverted prior to application to NAND gates 116 and 118, respectively.
Table I identifies the logic processing of pulse generator 112 for different values of delayed clock signals N2 and N3. As indicated by the last column in Table I, the output of pulse generator 112 (i.e., control signal WL_EN) is high, if and only if N2 is high and N3 is low. The logic processing of pulse generator 114 is similar to that in Table I, such that the output of pulse generator 114 (i.e., control signal BL_PCHGB) is high, if and only if N1 is high and N4 is low.
TABLE IPULSE GENERATOR PROCESSINGN2N3N3BNAND (N2, N3B)INV00110101011101001010
FIG. 2 shows a timing diagram showing two consecutive clock cycles of the processing of pulse-generation circuit 100 of FIG. 1, when operating at a clock frequency well below the circuit's maximum frequency. As indicated in FIG. 2:                Each rising edge of clock N1 triggers the initiation of a pulse in control signal BL_PCHGB;        Each rising edge of clock N2 triggers the initiation of a pulse in control signal WL_EN;        Each falling edge of inverted clock N3B triggers the termination of a pulse in control signal WL_EN; and        Each falling edge of inverted clock N4B triggers the termination of a pulse in control signal BL_PCHGB.As further indicated in FIG. 2, for each clock cycle, the rising edge of each pulse in control signal BL_PCHGB leads the rising edge of the corresponding pulse in control signal WL_EN by time T1, while the falling edge of each pulse in control signal BL_PCHGB trails the falling edge of the corresponding pulse in control signal WL_EN by time T2. As such, pulse-generation circuit 100 provides the desired timing relationship between WL_EN and BL_PCHGB at this relatively low operating frequency.        
FIG. 3 shows a timing diagram showing two consecutive clock cycles of the processing of pulse-generation circuit 100 of FIG. 1, when operating at a relatively high clock frequency. As indicated in FIG. 3, for the first clock cycle (CYCLE1):                The first rising edge of clock N1 triggers the initiation of a first pulse in control signal BL_PCHGB;        The first rising edge of clock N2 triggers the initiation of a first pulse in control signal WL_EN;        The first falling edge of inverted clock N3B triggers the termination of the first pulse in control signal WL_EN; and        The first falling edge of inverted clock N4B triggers the termination of the first pulse in control signal BL_PCHGB.        
Note that, at this high frequency, in the second clock cycle (CYCLE2), clock N1 rises before inverted clock N4B rises. As indicated in FIG. 3, as a result of this relationship, the rising edge of the second pulse in control signal BL_PCHGB is triggered by the rising edge of inverted clock N4B, instead of being triggered by the rising edge of clock N1. This results in the rising edge of the second pulse in control signal BL_PCHGB trailing, instead of leading, the rising edge of the second pulse in control signal WL_EN. This undesired result effectively limits the maximum frequency at which pulse-generation circuit 100 of FIG. 1 can operate properly.